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Design Intent Capture

Capturing Design Intent

CoverAll™ is a comprehensive suite of modules which capture design intent and automatically generates RTL code and the associated assertions and functional coverage properties. In addition, CoverAll™ generates testbench templates and scripts for use with industry standard simulator and formal verification tools.

 
Modules
The FC2Assert™ module takes easy to construct design intent flow and state diagrams and automatically creates assertion based properties:
Logic Assertions - each state in the flow diagram generates an assertion property
Path Covers - the path(s) to each state are captured with functional coverage points

FSMs - creates assertion properties for state transitions, holding terms and feedback paths. In addition, CoverAll™ creates sequences for all paths originating from the reset state.

The TD2Assert™ module takes easy to construct design intent timing diagrams and automatically creates sequences for each clock period and assertion properties from annotations on the diagram.

Please contact Sales for for information on all of Solid Oak's products as well as terms of usage on the optional Support Modules.

CoverAll™
FC2Assert
TD2Assert
RTLComposer
Ver2FC
Wave2TD

The RTLComposer™ module automatically generates synthesizable RTL from the same design intent flow diagrams.
 
Support Modules
CoverAll also includes 2 optional support modules for legacy code and 3rd party IP.
 
The Ver2FC™ module converts Verilog and SystemVerilog RTL into CoverAll™ compatible flow and FSM diagrams. These diagrams can be further processed by the FC2Assert module to generate comprehensive coverage metrics.
The Wave2TD™ module converts converts simulation waveforms captured in VCD or eVCD format into CoverAll™ compatible timing diagrams. These diagrams can then be processed by the TD2Assert™ module to automatically generate assertions and sequences.
   
The CoverAll™ Library  
The CoverAll Library is a collection of common structures, such as counters, muxes, registers and state diagram macros which speed the creation of the Design Intent flow diagrams.  
   
BindAll™  
The BindAll product takes the assertion files created by the CoverAll Enterprise Compiler and the design Verilog RTL and automatically creates bind modules for use in Simulation and Formal Verification. BindAll can also create a testbench template for SystemVerilog or uVM and script files for commercially available formal verification software1.  
 
1All tools support the PSL and SVA assertion languages and the Open Verification Library(OVL). BindAll™ and RTLComposer™ currently support Synopsys Magellan Hybrid Formal Verification and Mentor Graphics 0in Formal Verification products.
 


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