provide functional test points in the design,
simplify the detection of bugs earlier in the process,
can be used in both simulation and formal verification,
increase simulation observability,
and provide the metrics necessary for verification closure
Solid Oak’s innovative capture tool, CoverAll™, allows architects and designers to capture and document design intent in the form of flow, state and timing diagrams early in the process during the specification phase. These diagrams are automatically converted to functional assertions, cover paths and sequences in PSL or SVA languages or using Open Verification Library(OVL) checkers to reduce generation time and eliminate the errors of manual code and assertion creation.
With the optional RTLComposer™ module, designers can also automatically generate synthesizable RTL in Verilog or SystemVerilog, bind modules, module-level testbench templates in SystemVerilog or uVM, and formal verification scripts for industry standard Formal Verification tools.
For legacy designs and 3rd party soft IP, Solid Oak provides the optional Ver2FC™ and Wave2TD™ modules to convert existing Verilog/SystemVerilog RTL and simulation waveforms into flow, state and timing diagrams for automatic assertion generation with CoverAll™.
Design and Verification teams can also use Solid Oak's linux-based CoverAll Enterprise™ product to automatically create the same assertion, path covers, sequences and bind modules necessary for functional and formal simulation with SVA and OVL based assertions. CoverAll Enterprise™ automatically wraps PSL based assertions in vunit containers. In addition, CoverAll Enterprise™ automatically generates testbenches and tool scripts for industry standard formal tools.