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Verilog to Flow Charts
Capture Design Intent

The CoverAll™ Ver2FC™ module converts Verilog or System Verilog synthesizable RTL into functional flow diagrams.

 
Features

Generates CoverAll™ compatible flow charts

Automatically detects and extracts FSM constructs into flow charts

Supports the Verilog 2001 and System Verilog HDL languages

Runs as a Linux binary (CoverAll Enterprise) or on Windows platforms (CoverAll Professional)

Great for documentation of legacy designs and 3rd party IP: generated flow charts can be imported into MS Visio. Visio objects import directly into word processors such as Microsoft's Word and Adobe's FrameMaker

Professional (Windows) or Enterprise (Linux) versions

 
     
    CoverAll™
FC2Assert
TD2Assert
RTLComposer
Ver2FC
Wave2TD
Example Flow Chart    
RTL Code
Flow Diagram
always @(posedge clk or negedge nReset)
  if(~nReset)
    begin
        cnt <= #1 16'h0;
        clk_en <= #1 1'b1;
     end
  else if (rst)
     begin
         cnt <= #1 16'h0;
         clk_en <= #1 1'b1;
      end
  else if (~ena)
     begin
         cnt <= #1 clk_cnt;
         clk_en <= #1 1'b1;
     end
  else if (cnt==16'h0)
     begin
         cnt <= #1 clk_cnt;
         clk_en <= #1 1'b1;
     end
  else if (slave_wait)
     begin
         cnt <= #1 cnt;
         clk_en <= #1 1'b0;
     end
  else
     begin
        cnt <= #1 cnt - 16'h1;
        clk_en <= #1 1'b0;
     end
Flow Chart
 

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