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Waveform to Timing Diagram

Capture Design Intent

The CoverAllWave2TD™ module converts VCD or eVCD formatted simulation files into timing diagrams.


Generates CoverAll™ compatible timing diagrams

Supports industry standard VCD and eVCD formats

Graphical Interface allows user to view simulation waveforms, choose signals and time extents and extract selected waveform. Sequences are automatically extracted by the CoverAllTD2Assert module.

Extracted timing diagrams can be further edited; adding signal-to-signal relationships which are extracted as assertions.


Great for documentation of legacy designs and 3rd party IP: generated flow charts can be imported into MS Visio. Visio objects import directly into word processors such as Microsoft's Word and Adobe's FrameMaker

Windows version only.
Example VCD File    
Simulation File waveform display
VCD Code
Timing Diagram
	Wed Mar 17 16:39:11 2010
	QuestaSim Version 6.6_1
$scope module tst_bench_top $end
$scope module i2c_top $end
$var parameter 1 ! ARST_LVL $end
$var wire 1 " wb_clk_i $end
$var wire 1 # wb_rst_i $end
$var wire 1 $ arst_i $end
$var wire 1 % wb_adr_i [2] $end
$var wire 1 & wb_adr_i [1] $end
$var wire 1 ' wb_adr_i [0] $end
$var wire 1 ( wb_dat_i [7] $end
$var wire 1 ) wb_dat_i [6] $end
$var wire 1 * wb_dat_i [5] $end
$var wire 1 + wb_dat_i [4] $end
$var wire 1 , wb_dat_i [3] $end
$var wire 1 - wb_dat_i [2] $end
$var wire 1 . wb_dat_i [1] $end
$var wire 1 / wb_dat_i [0] $end
$var reg 8 0 wb_dat_o [7:0] $end
$var wire 1 1 wb_we_i $end
$var wire 1 2 wb_stb_i $end
$var wire 1 3 wb_cyc_i $end
$var reg 1 4 wb_ack_o $end
$var reg 1 5 wb_inta_o $end
Timing Diagram

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