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Flow Charts to RTL

The CoverAll™ RTLComposer™ module converts functional flow diagrams into synthesizable RTL. In addition, RTLComposer™ can generate a testbench template, bind module and formal verification scripts.

 
Features

Simple to Construct Flow Diagrams with included Shapes Stencil

Generates synthesizable RTL in Verilog or System Verilog

Runs as a Microsoft Office Visio Add-on

Generates a testbench template in System Verilog or uVM

Supports the Verilog 2001 and System Verilog HDL languages

Generates formal scripts for industry standard Formal Verification tools
When used with FC2Assert, creates a single source for documentation, RTL Code, Assertions and Functional Coverage. Generates Bind Module for formal and simulation so the RTL can remain untouched

Great for documentation of designs: Visio objects import directly into word processors such as Microsoft's Word and Adobe's FrameMaker.

 
Professional (Windows) version  
     
   

 

 
 
CoverAll™
FC2Assert
TD2Assert
RTLComposer
Ver2FC
Wave2TD
Example Flow Chart    
Page 1 Page 2  
Structural Representation of a Counter Top-level Block Diagram  


 

 

 

 

 

 

 

 

Download the Source file: cnt.vsd

module cnt (
        clk,
        nReset,
        rst,
        ena,
        slave_wait,
        clk_cnt,
        cnt,
        clk_en);

input		clk;
input		nReset;
input		rst;
input		ena;
input		slave_wait;
input	[15:0]	clk_cnt;

output	[15:0]	cnt;
output		clk_en;

reg	[15:0]	cnt;
reg		clk_en;

     always_ff@(posedge clk or negedge nReset) begin
         if(!nReset) begin
             cnt[15:0]<=16'h0;
             clk_en<=1'b1;
         end
         else begin
             if(rst) begin
                 cnt[15:0]<=16'h0;
                 clk_en<=1'b1;
             end
             else begin
                 if(ena) begin
                     if(cnt==16'h00) begin
                         cnt<=clk_cnt;
                         clk_en<=1'b1;
                     end
                     else begin
                         if(slave_wait) begin
                             cnt<=cnt;
                             clk_en<=1'b0;
                         end
                         else begin
                             cnt<=cnt-16'h1;
                             clk_en<=1'b0;
                         end
                     end
                 end
                 else begin
                     cnt<=clk_cnt;
                     clk_en<=1'b1;
                 end
             end
         end
     end
endmodule
`timescale 1ns/1ps
module tst_bench_top();
	logic		clk;
	logic		nReset;
	logic		rst;
	logic		ena;
	logic		slave_wait;
	logic	[15:0]	clk_cnt;
	logic	[15:0]	cnt;
	logic		clk_en;

cnt #() u0 (.*);
bind cnt ba_cnt #() u1 (.*);

/************************************************************************************
      THIS FILE IS AUTO-GENERATED BY COVERALL. DO NOT MODIFY ABOVE THIS LINE
************************************************************************************/
	initial begin
	    $finish();
	end
endmodule
`/*
 * RTL Composer Test Bench Options file for module cnt
 * Copyright (C) Solid Oak Technologies 2003-2012
 */

tb_cnt.v
C:\test_files\cnt\verif\cnt.sv
ba_cnt.v
+incdir+C:\test_files\cnt\verif
+libext+.v
+libext+.sv
module ba_cnt (
        clk,
        nReset,
        rst,
        ena,
        slave_wait,
        clk_cnt,
        cnt,
        clk_en);

input		clk;
input		nReset;
input		rst;
input		ena;
input		slave_wait;
input	[15:0]	clk_cnt;
input	[15:0]	cnt;
input		clk_en;

`include "counter.1.sv"
endmodule
/*
 * RTL Composer 0in run script for module cnt
 * Copyright (C) Solid Oak Technologies 2003-2012
 */

0in csl_cnt.scr
0in_prove \
	+0in_effort+unlimited \
	+0in_sanity_waveforms \
	+0in_timeout+30m \
	-log 0in_prove_cnt.log \
	-report 0in_prove_cnt.rpt \
	-db 0in_prove_cnt.db

0in_confirm \
	+0in_effort+unlimited \
	+0in_import_dbs+0in_prove_cnt.db \
	+0in_depth+400 \
	+0in_sanity_waveforms \
	+0in_timeout+1h \
	-log 0in_confirm_cnt.log \
	-report 0in_confirm_cnt.rpt \
	-db 0in_confirm_cnt.db
#
# RTL Composer compile_search_logic script for module cnt
# Copyright (C) Solid Oak Technologies 2003-2012
#

csl -sva -d tst_bench_top \
-f tb_cnt.f \
-ctrl control_cnt.v \
-tcs \
/*
 * RTL Composer 0in control file for module cnt
 * Copyright (C) Solid Oak Technologies 2003-2012
 */

module control;
// 0in set_clock  -period 10 -waveform {0 5}
endmodule


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