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Capture Design Intent

Tools for Design Intent Capture and
Assertion Based Verification

CoverAll Design Intent Capture
Automatic Generation of Assertions and Path Covers from Flow Diagrams
Automatic Generation of Sequences Assertions from Timing Diagrams
Automatic Extraction of Transitions, Holding Terms and State Path Sequences from Finite State Machine Diagrams
Automatic Generation of Synthesizable RTL from Flow Diagrams
Automatic Generation of SystemVerilog or uVM Testbench Templates
Automatic Generation of Formal Verification scripts
Ver2FC RTL to Flow Diagrams
Translate legacy RTL and 3rd party Intellectual Property into Flow and FSM Diagrams
Wave2TD Waveform to Timing Diagrams
Translate simulation waveforms into Timing Diagrams
 
 
News and Announcements

[10.30.2012]
Solid Oak is featured in EDA Digest Top Companies to Watch.

[07.15.2012]
Solid Oak Technologies announces the upcoming release of CoverAll™ 2012 in August. New features include:
- Automatic Generation of Synthesizable RTL from Flow Diagrams
- Automatic Generation of SystemVerilog or uVM testbench template
- Automatic Generation of Formal Verification tool scripts
- New GUI simplifies debugging of generated Assertions, Path Covers and Sequences

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